1. Field of the Invention
The present invention is directed to a method of determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. More specifically, the subject invention analyzes electrical properties of such SOI wafers such as mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material. Alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.
2. Background of the Prior Art
Silicon-on-insulator (SOI) substrate material is used as an alternative to standard “bulk” silicon substrates for creating integrated circuits. SOI substrates consist of a bulk wafer covered with a thin insulator, commonly known as the buried oxide (BOX), and further covered by a thin Si layer. SOI substrates are available in a variety of forms with varying silicon and insulator thicknesses and various processes for manufacturing the substrates. For example, SIMOX is a version of SOI material created by ion implantation of oxygen into silicon followed by high temperature heat treatment. Another version of SOI material is created by bonding one silicon wafer onto another with a SiO2 layer in between, followed by heat treatment and removal of most of one of the wafers in order to reduce it to a thin layer residing on the buried oxide layer and underlying silicon bulk region. Since there are various ways to fabricate SOI wafers and since they come in several forms, it is necessary to characterize the virgin starting substrates by a fast and convenient technique to separate good material from bad and good fabrication processes from bad ones.
One technique for accomplishing the material quality evaluation has been discussed in U.S. Pat. No. 6,429,145 for a Method of Determining Electrical Properties of Silicon-On-Insulator Wafers, and in U.S. patent application Ser. No. 09/770,955, filed Jan. 26, 2001, Measurement and Analysis of Mercury-Based Pseudo-Field Effect Transistors, in which two electrodes consisting of mercury are present on the surface of a SOI wafer and a voltage is applied between them. The bottom of the wafer is also contacted and acts as the gate of the field effect transistor, with the BOX acting as the “gate oxide.” Field effect transistors which use the buried insulator as the gate insulator and substrate as the gate electrode are commonly known as pseudoFETs. By analyzing the current voltage behavior for various combinations of voltages between these three electrodes, electrical properties such as the electron and hole mobilities, charge residing in the BOX, interface state densities, and doping level in the Si film can be determined. Further discussion of the technique is available in H. J. Hovel, “Si Film Electrical Characterization in SOI Substrates by the HgFET Technique,” Solid State Electronics 47, 1311 (2003). The HgFET has been very useful for quality control of SOI material with starting Si thicknesses of 400 to 500 Angstroms or above.
However, the mercury-based pseudoFET (HgFET) becomes difficult to use as the thickness of the Si layer is reduced below several hundred Angstroms because the threshold voltage of the HgFET can become comparable to the breakdown voltage of the underlying BOX. It also is not useful for multi-layer structures such as strained silicon on silicon/germanium on oxide where the electrical properties of the two layers act in parallel and the HgFET cannot separate them. The HgFET also cannot be used at temperatures more than a few degrees above or below normal laboratory ambient temperatures (15-25 degrees Celsius) so that no electrical properties as a function of temperature can be obtained. The HgFET cannot be used to detect light or to use light as a further evaluation technique because it is virtually always used in an upside down configuration due to the liquid mercury electrodes and therefore is in the dark. It also incorporates a chemical treatment step with hydrofluoric acid (HF) that increases the measurement time and reduces the number of separate devices that can be used to evaluate material over an extended surface area.
Replacing the mercury contacts with evaporated metal contacts overcomes many of these disadvantages. In addition, the metal can act as an ohmic contact which reduces the undesirable impedance represented by the electrode, whereas the mercury acts as a Schottky barrier which has high impedance. Ohmic contacts to silicon can be made with metals such as erbium (Er), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), platinum (Pt), gadolinium (Gd), neodymium (Nd), yttrium (Y), magnesium (Mg), and nickel (Ni) and combinations thereof. Er and Ti are commonly used as ohmic contacts to n-type silicon, as discussed in prior art such as Applied Physics Letters 55, 1415 (1989) and Applied Physics Letters 38, 865 (1981) while Au, Ag, Al, and Pt are used as ohmic contacts to p-type silicon. In the evaporated metal pseudo-FET, also commonly known as a RingFET, it is desired to make an ohmic contact to the carrier type created by the FET behavior regardless of the doping type of the silicon layer. Thus, Er- and Ti-based contacts are made for obtaining the electron channel properties created by FET action regardless of whether the material is p-type or n-type, and similarly Au-, Al-, Ag-, Mg-, and Pt-based contacts are used to obtain the hole channel properties created by FET action whether the material is n-type or p-type. This differs from the prior art where Er and Ti are used to make ohmic contacts to n-type material and form Schottky barriers to p-type material, and are therefore not used for making ohmic contacts to p-type silicon. In the ringFET, Er- and Ti-based metal contacts are used as ohmic contacts to the electrons in the inversion layer, even though the silicon is routinely p-type.
Pseudo-FET devices for SOI material measurements as a function of temperature using point contacts or evaporated Al contacts have been described in Rossel et al, Electrochemical Proceedings Vol. 2003-05, page 479. No mention is made of double gate devices, devices with surface oxides, or other metal contacts. The same Conference Proceedings contain technical papers dealing with double gate devices and with strained Si/SiGe devices. In these cases, integrated circuit processing is needed to fabricate devices capable of yielding electrical properties, including ion implantation to dope the layers and high temperature annealing. The resulting properties are therefore of processed material rather than the virgin starting material. In the present invention, no ion implantation or high temperature annealing are used, and no photolithography is required, although one simple photolithography step can be used to optimize the device if desired.